For a long time, in order to achieve a higher chip density, a faster working speed and a lower power consumption, a feature size of a MOSFET (metal-oxide-semiconductor field effect transistor) is continuously scaled down according to Moore's law, and a working speed of the MOSFET is faster and faster. Currently, the feature size of the MOSFET has reached a nanometer level. However, a serious challenge is an emergence of a short-channel effect, such as a subthreshold voltage roll-off (Vt roll-off), a DIBL (drain-induced barrier lowering) and a source-drain punch through, thus increasing an off-state leakage current. Therefore, a performance of the MOSFET may be deteriorated.
In addition, a leakage may be alleviated by a SOI (silicon on insulator) structure, however, a heat conductivity of a SiO2 insulating layer in the SOI structure is low, so that a heat generated in a channel in a small size device may be difficult to dissipate. Therefore, a heat dissipation of the SOI structure may be inhibited.
Therefore, for a conventional device, large leakage and difficult heat dissipation are main constraints for scaling down.